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> > Source to Drain leakage-> No > That is what we had for a while already, and which is referred to as > "subthreshold-leakage", right? This is the leakage current through the two back to back diodes that exist between the Source & Drain. Sub-threshold leakage sound right to me. I was assuming a long channel device, so the forward leakage or "off" current (for the long channel) would be orders of magnitude lower than the "on" current. > Trending as expected for 90nm? I seem to recall that as dimensions are/were shrinking, the main concern was the gate leakage. The leakage in the channel can be reduce "simply" by increasing the doping concentration (in the channel). So a npn long channel MOSFET evolved into a n+p+n+ MOSFET. > > Gate to Source leakage-> Yes > > Referred as "gate-leakage", which was orders of magnitudes lower for > previous nodes, but is expected at 90nm in the same order of magnitude as > subthreshold leakage, right? I'm not totally up to speed with the current technology. But, tunneling is effected by barrier height and thickness, so as the channel shrinks the leakage current increases and same thing if the gate dielectric thickness decreases. So the answer is that it ultimately depends on the exact geometry of the device (channel length and gate dielectric thickness). > Any indications that this gate-leakage is actually exceeding the > expectations relative to subthreshold-leakage (Oder of magnitude higher > already??) at 90nm? Gate leakage seems to be the main concern as per publications so new "high k"/"high kappa"/"high epsilon" dielectrics are being researched (OxyNitride, HfO2, and ZnO2 gate dielectric). But this is an assumption solely based on the papers that I have seen/read. Hope this helps. Dwayne PS I'll be leaving for the South Pacific on Tuesday Nov. 4th for 6-12 months. So if you have more questions, please ask them sooner rather than later.
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