Re: Pspice compatibility: Bus representation in subcircuit calls

On 01 Dec 2003 20:02:53 GMT, "Mike Engelhardt" <[EMAIL PROTECTED]>
wrote:

>Larry,
>
>>>It was a common practice in velum drafting days.
>>>For example, you have two data busses, read and
>>>write.  They both a conductor D3 but are different
>>>nets as they go to different pins on the memory
>>>parts of old.  The problem is that the computer
>>>CAD tools don't allow this to be drafted and now
>>>people got used to the artificial limit.
>>
>> Geesh.  Talk about an lvs nightmare.
>
>But it has nothing to do with lvs.  You
>still confuse schematic caputure capabilities
>with SPICE and lvs.  The netlister interfaces
>between these.  The problem is that the computer
>CAD tools don't allow things to be drafted and
>now people got used to the artificial limit.
>
>--Mike
>

We still seem to be running in circles.  In my mind schematic capture
must be able to do the following things:

(1) Create a netlist readable without ambiguity by the Spice engine.
(2) Yet present a useful visual representation of the circuit...
humanly readable; AND handle hierarchical and bussed designs.
(3) Have a user-friendly GUI to make drawing convenient.
(4) Allow placing "markers" on the schematic that then show waveforms
in an appropriate viewer.
(5) Show operating point data (voltages and currents) directly on the
schematic, for debugging, if desired.
(6) Be able to produce LVS netlists in formats readable by many layout
tools.

PSpice Schematics can do *all* of the above ;-)

                                        ...Jim Thompson
-- 
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
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