Potential Bus Contention Between Flash reads and SDRAM writes

Hi there,

Anyone has any ideas on the above TMS320VC5470 Errata?

It says on reads from Flash the output enable to data bus three-state
could be slow enough to cause reliability contention with SDRAM write
operation.

Its workaround solution is to avoid by using the internal SRAM to run
code and intermediate data from the FLASH. Also all stacks should be
located in internal SRAM.

In view of this, since the internal SRAM is only 16k, and my program
is way above it, what options do I have?

Anyone has any opinion on this?

Thanks!