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[EMAIL PROTECTED] (Vic) wrote in message news:<[EMAIL PROTECTED]>... > Hi, > TMS..54x have register 'SWWSR', high 4 bits define 'wait cycle for IO space'. > I set 0x7000 for use 70 nsec flash. > > Cheers Hi all, thanks for your generous reply.... However, the problem persist... As far as I know, correct me if wrong, SWWSR is for the DSP, I am using the ARM7 for the interfacing. I have configured the CS-reg, BS-config-reg with all kinds of wait states... The weired part is that, with the same config, it can run on the JTAG (under SRAM) mode. But when switched to the Flash, the problems appeared... Any clues... Thanks in advance!
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