Re: No Transmission Gate in Standard Cell Library

On 9 Sep 2003 21:05:47 -0700, [EMAIL PROTECTED] (Hooman)
wrote:

>[EMAIL PROTECTED] (Henning Bahr) wrote in message news:<[EMAIL PROTECTED]>...
>> Hi all,
>> 
>> I can't find any Transmission Gates in my ASIC standard cell library.
>> Is that common? If it's common, why aren't they included?
>> 
>> Cheers,
>> Henning
>
>Hi,
>
>I have the same question. Why there is no TG in any standard cell
>library and how it could be added to a library?
>
>Regards
>Hooman

Maybe you're not checking the right cell type. Look for a Tri-State
buffer in your library. Almost all standard cell libraries have
internal tri-state buffers. If your library doesn't include it, you
can design the cell yourself, do a LEF for it for P&R. You also need
to simulate it in spice to extract the timing values.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations