Re: name collisions

I am just guessing here, but you could try the following:

Use time/date for randomization of the name.  Makes the
name messy, but it is unique (you have to use numbers).

Alternatively, use CompanyName_ProjectID_ModuleName

I am not sure if there is going to be an elegant solution.

Sumit Gupta

John Eaton <[EMAIL PROTECTED]> writes:

> Back in the good ole days when asic design teams
> were small and we designed everything ourselves it
> was easy to manage name space collisions.
> 
> Now we are incorporating more and more blocks
> of 3rd party IP into our chips and we really
> have no way to prevent multiple vendors from
> creating sub modules using the same name.
> 
> Verilog have some use library commands that would
> allow us to force modules to only draw from their
> own local files but I am trying to figure out how
> to add the same functionality to synopsys.
> 
> Anybody have a good solution?
> 
> 
> 
> John Eaton
> 
>