Re: Pipeline flushing in processors

Ameet wrote:

> Wehnever a interrupt or any other exception occurs in superscalar
> processors, the pipeline is "flushed". Can anybody guide me on these
> two questions:
>
> 1. When is a pipeline flushed? For some interrupts (precise
> interrupts) the execution continues normally;
> so what are the instances when the pipeline is flushed?

> 2. How is this implemented? When designing a pipeline using a
> HDL/state machine what steps are to be followed to flush the pipeline.

> 3. Is there a detailed description of pipeline flushing available for
> any modern processor architecture (IBM/SPARC/x86)

A google search for "360/91" "pipeline"  will find everything you need 
to know about pipelined processors.   You only asked about precise 
interrupts, these will also include the effects of imprecise interrupts.

Apparently it is implemented in 120,000 gates of ECL.  I didn't know the 
number before.

-- glen