Re: 1teraflops cell processor possible?

On Fri, 28 Nov 2003 01:53:02 GMT, Andrew Reilly
<[EMAIL PROTECTED]> wrote:

>On Wed, 26 Nov 2003 22:55:34 -0500, Robert Myers wrote:
>> In a streaming architecture, you fetch data from somewhere, you do
>> something with it, you do something else with it, you do something
>> else with it, you do something else with it, ad nauseum, until you
>> have absolutely run out of operations you can stream together.
>> *Then*, and with great reluctance, you bear the cost of putting the
>> data where you will need to bear the cost of fetching it again.
>
>What makes you think that Blue Gene *isn't* a streaming
>architecture?  Or a systolic one, or whatever?  As long as the
>"do something with it" part is sufficiently general-purpose, it
>comes down to how you program the thing.
>
Well, no it doesn't.  It comes down to what kinds of facilities for
interprocessor communication exist, and I've heard nothing about Blue
Gene to indicate that processor to processor streaming is possible.
If it is, perhaps someone will provide a link or a clue.

>Sure, any of these cluster-in-a-box systems, particularly the
>cache-coherent ones, can also be programmed as (approximations
>of) conventional SMP systems (in the queuing theory sense), but
>we all know where the bottlenecks are, and how best to push the
>processors towards peak throughput: minimise communications.
>The trick is formulating the algorithm for arbitrary problem X
>to suit.  I don't see that it's a failure of any sort to try to
>get to "there" from "here" in a comfortable, gradual way.
>
If you need to haul data a significant portion of the chip width to
use it once or twice, you're going to get killed on energy costs
relative to a true streaming architecture.  You can't program that
away.

>Legacy code and legacy coding practices exist.

Yes, and if some people had their way, apparently we'd still be
writing x86 code well into the next century.

I don't know in what area you work or have worked, but HPC codes are
constantly being rewritten to accommodate new architectures.

RM