Re: Will Prescott work on Win64?

Linus Torvalds <[EMAIL PROTECTED]> wrote in message news:<[EMAIL PROTECTED]>...
 
> It's a question of having advantages of a mass market. If AMD continues to
> produce 32-bit versions of the Athlon chip (regardless of whether they base
> it on the old K7 architecture or just a cut-down K8) they automatically
> kill off interest in their 64-bit architecture.
...  
> So if you see AMD actively pushing their 32-bit offerings next year, you'll
> know that the Athlon64 is in deep trouble. 

Since I have been following x86-64 as a technology closely for a
while, and AMD as a stock for years, let me contribute what I know on
this subject.

First, way back when, AMD had two Hammer designs, Clawhammer with a
256k L2 cache, and Sledgehammer with dual-DDR channels and a 1 Meg L2
cache.  But a funny thing happened on the way to market, one of those
Duh! things that is obvious in retrospect.  The design of the on-die
memory management software is such that ALL data being accessed from
main memory goes into L2 cache.  This has some advantages for paging
and writing to disk, but it also means that when the graphics card
reads large texture files, they go into L2 on their way to the
graphics chip.  Result?  Too much cache pressure when running 3d games
on a 256k L2 cache Hammer.

Once AMD discovered this issue they designed a varient of Clawhammer
that was apparently intended to fix this problem.  This design was
called Paris.  When the Athlon64 was launched the market expectation
was for Paris chips to begin with, then a high-end variant based on
the Sledgehammer core.

What happened was that AMD started talking just before launch about a
manufacturing glitch, and the two introductory Athlon64 chips were the
Athlon64 FX-51, a Sledghammer in 940-pin packaging, and Athlon64
3200+, a Sledgehammer chip in a Socket 754 package, with only one DDR
channel available (due if nothing else, to the packaging).

As of this month, AMD has a new product roadmap,
http://tinyurl.com/a23  Notice that AMD now has a third new design as
the 0.13 micron Athlon64, called Newcastle, and Paris is to eventually
be sold as an Athlon XP.

(What follows is speculation, but informed speculation.)  What is
going on?  My guess is that the fix in Paris provided decent graphics
performance in 32-bit mode, but that in 64-bit mode a 256k L2 cache
was still too small.  So Paris will be sold as an Athlon XP in Socket
754 packaging.  I don't know whether Paris will be sold as a 32-bit
only chip, or a chip with best performance as a 32-bit CPU, but with
64-bit addressing available.  In other words, on Sledgehammer, and
presumably Newcastle, Athens, etc., 64-bit code runs faster than
32-bit code (mostly due to the added registers), while on Paris the
opposite is true due to cache pressure.  My guess is that Newcastle
will have a 512k L2 cache, but it may be 1 Meg.  Winchester, the 90 nm
version of Newcastle is more likely to have a 1 Meg cache.  (But San
Diego, the 90 nm Athlon64 FX will have a 1 Meg cache, and dual-DDR, so
it will be the chip of choice for those who want performance.)

Whew! A lot of Hammer code-names in there with not much information
available without signing an NDA.  But the important things to note
are:  AMD is abandoning the Socket A that has been used since
Thunderbird.  The last Socket A parts will be manufactured next year,
new wafer starts may end as soon as 2Q04, but will certainly end in
3Q04, with the last volume sales in 4Q04.

Second, the Athlon XP family will be Hammer compatible.  If not with
Paris and Dublin next year, with Polermo and Trinadad in 2005.  It is
possible right now to separate the added registers from the 64-bit
address support.  The 64-bit address support in Hammer depends on, of
all things, the PAE flag. There is a separate bit that indicates
64-bit long mode with the added registers.  I don't know how much of
the current PAE pain occurs if you try to use it with a Hammer chip in
"compatibility" 32-bit mode.  I don't even know if it is currently
possible.  But either Intel could go this route with Xeons, or AMD
with the Athlon XP family, and there would be 64-bit addressing
support without the added registers.  (The current non-FP registers
would need to be 64-bit though.)

So my suspicion is that Linus has it right.  AMD is going to leave
32-bit only x86 chips in the dust, while continuing to support
compatibility mode software.  In fact, with current Hammer chips once
you are running a long-mode OS, you are ahead of the game. 
Compatibility-mode user processes can have a 4 Gig address space for
non addition cost.  I don't know how they will distinguish the Athlon
XP chips from the Athlon64 chips, but I expect it to be on performance
and only performance.