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"David Wang" <[EMAIL PROTECTED]> wrote in message news:[EMAIL PROTECTED] > lmurata <[EMAIL PROTECTED]> wrote: > > Han de Vries has claimed it is not practical to design a processor > > that has a peak performance of 1tflops using a 65nm process. Well, > > look at the pdf below. It claims a stream processor can be designed > > with a peak performance of 128Gflops using a 90nm process. Could he be > > also wrong about the feasibility of a 1tflops cell processor? > > > http://www.sc-conference.org/sc2003/paperpdfs/pap246.pdf > > If you keep the same die size, you get 2X the "area" in going > from the 90nm process to a 65nm process. > > Assume that you can double the number of execution units, then > you can get to 256 Gflops. > > If you further assume that you can get 1.5X the frequency from > the processor shrink, you can get to 384 Gflops. > > Given these assumptions, you're still a bit shy of 1 Tflop. > > -- > davewang202(at)yahoo(dot)com Don't forget the difference between "paper shows can be designed" and "is practical to design..." The device has to be manufacturable (die size), coolable, powerable, and of wide enough interest to be worth dumping many millions of dollars into design and fab. I wonder what the NRE will be at 65 nm? del cecchi
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