Re: Call-gate-like mechanism

"Anne & Lynn Wheeler" <[EMAIL PROTECTED]> wrote in message
news:[EMAIL PROTECTED]
> "Glen Herrmannsfeldt" <[EMAIL PROTECTED]> writes:
> > Is this a comment about the S/360 interval timer, or about an OS
> > that uses it?  MVT will use STCK on machines that have one.  Also,
> > the interval timer was defined with extra bits for possible increase
> > in resolution later, and it might be that some processors
> > implemented those.  I presume there is no NTP implementation for
> > MVT, though, STCK or interval timer.
>
> the problem with the 360 timer was that it updated storage 32bits at
> location decimal 80. most 360s had 3.3mil resolution (tic'ed 300 times
> per second bit 8, or bit 24 depending on which direction you are
> counting from) ... but (at least) the 360/67 had high resolution timer
> that ticked the low order bit every 13microseconds (256*300 times per
> second, in part for things like time-sharing applications).
>
> 370 added high resolution timers in the hardware that were accessed
> via special instructions. low resolution timer in location 80 was kept
> for awhile ... but was depreciated.

(snip).

> One of the early bugs we ran into was that if the timer is not able to
> update location 80 between two timer tics ... it redlights and hangs
> the machine. Having a controller hold the channel and therefor the
> main storage bus for longer than a timer tic interval (13.mics on
> 360/67) would redlight and hang the machine.

I thought they would store up some number of missed counts, until it could
get to the timer again.  Though if you exceed the number then I can see
redlighting.  Especially with a fast timer.

For the 360/30  (the Functional Characteristics manual happens to be sitting
here):

   "The Model 30 timer (special feature) operates at a fixed cycle rate of
16.7ms (60 cycle power supply) or 20 ms (50 cycle power).  The microprogram
controls the decrementing of the timer."

"The interval timer microprogram requires 7.5 to 13.5us (10 to 18 us in a
CPU with 2us RW cycle) per count depending upon whether there is a carry in
the count.  Thys cycle occurs asynchronously with respect to the stored
program and I/O operation."

"Back-up register is provided with the timer feature to accumulate
automatically a count of up to 16 intervals of time, if main storage cannot
be accessed because of prolonged I/O or direct control operations.  This
feature permits a delay of up to 277ms between timer count references
without loss of the count."

It does not say what happens if the 16 intervals are exceeded.


(snip)

> detailed discussion of tod, clock comparator, & cpu timer on current
> generation machines (although I don't think the definition has changed
> since the original 370 some 30 years ago):
>
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/DZ9ZR001/4.6?SHEL
F=DZ9ZBK01&DT=20020416112421

> and description from CPU Timer:
>
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/DZ9ZR001/4.6.4?SH
ELF=DZ9ZBK01&DT=20020416112421


It may have changed slightly.   The architecture now has a 128 bit counter.
Some of those bits are used for the 64 bit counter instructions, possibly
with slight changes to the meanings of those bits.

I don't know what this has to do with NTP, though.

-- glen