Re: Call-gate-like mechanism

Anne & Lynn Wheeler wrote:
> 370 (30 some years ago) introduced a 64bit timer infrastructure that
> had time of day clock register, a clock comparator register (value
> that when TOD matched caused an interrupt), and a cpu timer register.
> with low order bit of the high word defined as slightly more than one
> second (1024/1000).
[snip]
> and description from CPU Timer:
> http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/DZ9ZR001/4.6.4?SHELF=DZ9ZBK01&DT=20020416112421
>
> The CPU timer is a binary counter with a format which is the same as
> that of bits 0-63 of the TOD clock, except that bit 0 is considered a
> sign. The CPU timer nominally is decremented by subtracting a one in
> bit position 51 every microsecond. In models having a higher or lower

OK, now I'm confused:

Is the timer ticking at (fractional) milliseconds (1024/1000 seconds) or 
at microseconds?

I believe Hack was the one who sent me the 360 asm code that converts 
between the micro- (or milli-?) second counter and Y-M-D H:M:S.ccc 
format time.

> resolution, a different bit position is decremented at such a
> frequency that the rate of decrementing the CPU timer is the same as
> if a one were subtracted in bit position 51 every microsecond. The
> resolution of the CPU timer is such that the stepping rate is
> comparable to the instruction-execution rate of the model.

That is nice, makes it possible to write portable timing code with 
maximally good resolution across orders of magnitude cpu frequency 
variation.

Terje

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"almost all programming can be viewed as an exercise in caching"