Re: Will Prescott work on Win64?

In <[EMAIL PROTECTED]> Terje Mathisen <[EMAIL PROTECTED]> writes:

>Dan Pop wrote:
>
>> In <[EMAIL PROTECTED]> Terje Mathisen <[EMAIL PROTECTED]> writes:
>> 
>>>Dan Pop wrote:
>>>>The traditional Cray vector processors fall into this category.
>>>
>>>In the paragraphs you snipped, I mentioned how being allowed to use the 
>>>64-bit MMX registers to address the 36-bit physical address range of 
>>>some x86 cpus would have made them (ugly) 64-bit cpus.
>> 
>> Which doesn't make any sense, of course.  "The largest flat address
>> range you can easily handle" in this scenario is still 36-bit, period.
>
>By "handle" I meant which size would a pointer be, and how would I do 
>address arithmetic on it. I don't care how many of the bits are actually 
>brought out on the memory bus, only that the total is large enough for 
>the task I'm doing.

But that total is still not (necessarily) determined by the size of the
registers used for computing the address.  See my examples. 

>> You were not consistent with your own definition.  According to your
>> definition, that would make it a 36-bit processor.
>> 
>> You're confusing the integer arithmetic capabilities of the CPU and its
>> addressing capabilities.  It makes no sense to talk about 64-bit
>> addressing, unless the architecture defines a biunivocal relationship
>> between the address range and the range of values representable in a 
>> 64-bit CPU register.
>
>I don't think I'm confused, but I seem to be confusing, at least to you.

Regardless of what you think, you are confusing arithmetic capabilities
and addressing capabilities.  You have provided ample proof in this
thread.  Your definition is broken for 8-bit CPUs and for many 64-bit
CPUs, as well as for a fair number of historical architectures.

Dan
-- 
Dan Pop
DESY Zeuthen, RZ group
Email: [EMAIL PROTECTED]