Re: 400 Mb/s ADC

[EMAIL PROTECTED] (Jeff Peterson) wrote in message news:<[EMAIL PROTECTED]>...
> We are building a new radio telescope called PAST
> (http://astrophysics.phys.cmu.edu/~jbp/past6.pdf)
> which we will install at the South Pole or in Western China.
> 
> To make this work, will need to sample (6 to 8 bit precision) dozens
> of analog voltages at 400 Msample/sec and feed these data streams into
> PCs. One PC per sampler.
> 
> The flash ADCs we need are available (Maxim), but we are finding it
> difficult to get the data into the PC.

You should definitely talk to High Energy Physics People. Like the
STAR experiment at BNL or ALICE at CERN. Talk to the data aquisition
and Level 3 Trigger people there. You probably can just buy boards
with fast links and DSPs from them.

If you want to design it yourself, here are some comments:
1)
If you use a busmaster device you and you want to read data with 50%
duty cycle you can buffer the events in your readout board and reduce
the data rate to 200MByte/s. You add one event of latency.

2)
The fastest slots on a PC Mainboard are the memory expansion slots.
It's an easy to design hardware interface and if you use a server
mainboard with multiple memory channels you get a hell lot of
bandwidth. I remember seeing a cryptoaccelerator on a DIMM somewhere
and SUN used to place graphics boards in memory slots.

3.
If your political environment is similar to high energy physics, than
if you can reduce the duty cycle it does not really matter how
expensive the readout boards are. With a large FPGA on a PCI board you
can try to perform all computations on the board and achieve a 100%
duty cycle.

Kolja Sulimma