Re: Schematic simulation and then FPGA programming?

Hi David Brown ([EMAIL PROTECTED]), you wrote:
>
>"John K." <[EMAIL PROTECTED]> wrote in message
>news:[EMAIL PROTECTED]
>>
>> Hello people,
>>
>> I am strictly a schematic user, please don't turn this thread
>> into a "but HDLs are really better!!".
>
>I know you don't want to hear this, but I'll try to give a reasoned
>arguement rather than a blanket statement.

I always liked reasoned arguements.. go ahead. :)


>As fpgas get bigger and bigger, there is no doubt that most designers are
>using hdls rather than schematics (or sometimes a mixture).  For big
>systems, there are few that are made using pure schematics.

I'm not saying you're wrong, but I don't understand what makes inherently
more difficult to use schematic than HDL as projects get larger.

I think in a "object oriented" way.. for example, I make Flip-Flops from
NAND gates. So I get a Flip-Flop object. I make registers/latches from
Flip-Flops, so I get a Latch object. I mean, complexity can naturally
get encapsulated and encapsulated, till you have a whole ALU, or a whole
processor, etc.. and your schematic always looks simple (circuits and
subcircuits encapsulated into virtual devices).
I don't have much experience with current schematic software (I used
mostly my own.. nothing fancy anyway, but worked well for encapsulating
at least), but I see no reason why schematic based (using macros) should
be any slower or more confusing than HDLs?

I can only think about one problem: simulation gets slower and slower.
But neither this must be true: if simulating a whole Latch via NAND
gates may be slow, after I know it works well and I have its timing
characteristics known, I can encapsulate also them into the "black
box" and simulation of a Latch will be very quick.. having just to
simulate the function (and delays) from input to output.

HDL's IMHO are very confusing, hardware wise. A schematic is much more
natural and intuitive. IMHO of course.

On the other hand the non-intuitive, too abstract HDLs will make you
design things that then in silicon are very inefficient.. will not
give you a good "big, real picture" of what you're doing, etc..


>This means that
>tool designers will put far more effort into the HDL support for their tools
>than schematic support.

Yep, and that just makes me think that the problem is not in the
schematic idea per se, but in the current software.

This is a typical situation for the usual "no programs satisfied my needs,
so I wrote my own". :D

Too bad I don't have that much free time.. so I'd prefer to stick with
something already available. I have my own schematic based simulator but
its editor is nothing mature at all, and it's missing many features.


>I haven't tried doing schematic design for an fpga,
>so I can't comment directly, but I have heard complaints on this newsgroup
>about the quality of the schematic tools for some fpgas.  It also means that
>if you are learning about fpgas, there is a lot to be said for looking at
>using HDLs - you are going to get better tool support, better online
>tutorials and introductions, and end up with a more useful skill.

Right, I feel much "out of the world" by not following the HDL route.. but
I can't help.. it's a hobbyst project and I have to enjoy it. This definitely
means "no HDLs". ;)


>If you really want to use schematics, it may be that the best route is to do
>the design using your current schematic design software and then use edif
>netlists to import it into the fpga toolkit - I'm sure there are others in
>this group who could give you ideas there.

That's very interesting. Please, can you elaborate more on this?

You mean that I could do schematic entry and schematic simulation on any
software that is able to save in EDIF format? What would be the best software
(simulation-wise) capable of it, can you name a few?

And then I could load the EDIF file into Webpack (?) and from there what
should I do? Is further simulation (more FPGA-device targetted) possible?

How could I express things like block-ram in the former schematic program,
if it's quite totally separed from the back-end tools?

Thanks for your time!
John