Re: what's the problem?

[EMAIL PROTECTED] (algous) wrote in message news:<[EMAIL PROTECTED]>...
> I write a module as below. Let's look the last ALWAYS block.
> In the case statement, It worked not as expected when I replaced the
> binary  form's condition(2'b00,2'b01,2'b11, etc) with 
> Parameter(IDLE_PHASE,NONSEQ_PHASE, SEQ_PHASE) each other, the FSM's
> state(ahb_state) always loop in the last state(default 2'b11). while
> writing as below, It seemed worked well. Simulating in the modsim SE
> PLUS 5.6, the waves showed the value  of ahb_state always be 2'b00.
> whys?

[snip code]

You might get a better response if you ask in comp.lang.verilog.

--a