Re: Design analyse methods

ALuPin wrote:

> Simulation might be a good first step in order to prove
> first correct functionality

Best first, second and third step.

> but what if there are
> some components which cannot be reproduced my models so
> easily? 

Inside the FPGA, don't use vendor core generators.
Write your own code that infers what you need.

For memory and other external parts, choose devices
with free models or write some code.
You may not need a very fancy external model to verify
your own synth code.

Once you're done, you can "probe" wherever
you like with sim waveforms, and have the
freedom to make changes fearlessly.


   -- Mike Treseler