Re: Xilinx Virtex-II: DCM int & ext feedback

Gernot Koch wrote:
> Hi,
>
> I've tried to understand exactly which clocks a DCM will phase align when I do 
> external or internal feedback by the book. I've read every bit of documentation 
> I could find, but came out empty-handed. So maybe someone out there can help me 
> out...
>
> This is the structure I have for internal feedback:
>
> module int_fb(clki, clko);
>   input clki;
>   output clko;
>   wire clki_buf, clk_fb, clk_2x;
>   assign clko = clk_fb;
>   IBUFG ibufg0(.I(clki), .o(clki_buf));
>   DCM dcm0(.CLKIN(clki_buf), .CLKFB(clk_fb), .CLK2X(clk_2x));
>   BUFG bufg0(.I(clk_2x), .O(clk_fb));
> endmodule
>
> Which wires are phase-aligned clocks here?

The output of the BUFG (clk_fb) will be phase aligned with your input 
clock (clki).  By connecting to the CLKFB input, the DCM removes the 
phase offset introduced by routing, the BUFG, and the DCM itself.

This results in the rising edge internal to the FPGA occurring at nearly 
the same time as the rising edge of the clock feeding the FPGA... hence 
you maintain a completely synchronous system.

> External feedback:
>
> module ext_fb(clki, clkfb, clko);
>   input clki, clkfb;
>   output clko;
>   wire clki_buf, clk2x, clkfb_buf;
>   IBUFG ibufg0(.I(clki), .O(clki_buf));
>   IBUFG ibufg1(.I(clkfb), .O(clkfb_buf));
>   DCM dcm0(.CLKIN(clki_buf), .CLKFB(clkfb_buf), .CLK2X(clk2x));
>   OBUF obuf0(.I(clk2x), .O(clko));
> endmodule
>
> clko is connected to clkfb outside the FPGA.
> I've omitted reset and locks for simplicity.
>
> Again, which wires are phase-aligned clocks here?

clko, at the point on the trace that it enters the FPGA, will be phased 
aligned with your input clock (clki).  If the trace continues on for 
another six inches past the FPGA pin, the end of the trace will of 
course have an additional small phase offset due to flight time.


HOWEVER, Xilinx is considering changing the rules so that you can't do 
what you've coded up in your two examples, at least in a V2-Pro.  The 
restriction they are considering is that CLKFB can't come from a CLK2X 
output anymore.  For off-chip deskew, this really throws a monkey wrench 
into things.  I don't know if it is too late (or useful) to complain to 
your FAE about this or not.

> Also related: what does the DESKEW_ADJUST attribute do? The documentation I 
> found says only how you set it, but not what it does...

The first two hits when typing in DESKEW_ADJUST in the Xilinx search 
page seem to explain it pretty well:

http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0086_39.html
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14743

   Marc