Re: Exact Timing Constraints vs. Over-Constraining

Larry Doolittle wrote:

> In article <[EMAIL PROTECTED]>, Phil Hays wrote:
> > I try to enter the constraints that exactly match the timing that the
> > design will need to function, including board delay, loading delay,
> > clock jitter and clock skew.
> 
> Don't forget metastability slack.  In theory it does not apply to the
> purely synchronous nets; in practice I don't want to go through the
> work of separating them out, and it's a good excuse to add one more
> conservative assumption.

Yes.  When crossing clock domains, make a time group of the synchronizing
flipflops and make a FROM TO style constraint for just those flipflops.

While my current designs are slow by my standards (125 MHz fastest clock 
in a Virtex 2),  I can't afford to reduce the periods by 3 ns, as that 
is a large fraction of an 8 ns period!


-- 
Phil Hays