Re: Exact Timing Constraints vs. Over-Constraining

>Temperature, Vcc, and process variations are already (and have always
>been) covered by the worst-case assumptions behind the Xilinx timing
>analyzer numbers.

But they don't know anything about the input clock jitter.

In the old days, we mostly ignored clock jitter.  Or rather
build clock distribution systems with low enough jitter that
it was reasonable to ignore it.

I think part of the round-down that people are doing today
is to cover the clock jitter that they haven't thought about much.
It's interesting/important at todays higher speeds.

Quick.  How much jitter on the clock going into your PCI card?
(Is that even covered in the specs?)

Don't forget Ray's stories of SSO adding to the jitter.

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