Re: Exact Timing Constraints vs. Over-Constraining

On Tue, 2 Dec 2003 16:07:51 -0600, Richard Iachetta <[EMAIL PROTECTED]>
wrote:

>In article <[EMAIL PROTECTED]>, [EMAIL PROTECTED] 
>says...
>> In article <[EMAIL PROTECTED]>, Robert Sefton wrote:
>> > "Larry Doolittle" <[EMAIL PROTECTED]> wrote in message
>> >>
>> >> Don't forget metastability slack.  In theory it does not apply to the
>> >> purely synchronous nets; in practice I don't want to go through the
>> >> work of separating them out, and it's a good excuse to add one more
>> >> conservative assumption.
>> > 
>> > What is metastability slack and how do you apply it? Do you mean you
>> > over-constrain your clock periods slightly to expand setup margins?
>> 
>> Yes and no.  Yes, I over-constrain my clock slightly (Peter Alfke's
>> nominal number for modern chips and "typical" applications is 3 ns).
>> The interpretation is to allow time after the clock edge for each
>> flip-flop (that has an asynchronous input) to "choose" which state
>> to land in.
>
>Larry, your clocks must be pretty slow if you can afford to add 3 ns to every 
>path in the design instead of just the few async boundary paths.  I would call 
>that majorly, not slightly, over-constraining the design.

Yes.  I have some 1.6ns clocks in my current design.  It would be a
bit hard to make the constraint 3ns tighter.

Moral: avoid cookbook solutions.

Regards,
Allan.