Re: Exact Timing Constraints vs. Over-Constraining

Larry Doolittle wrote:

(snip)

> Yes and no.  Yes, I over-constrain my clock slightly (Peter Alfke's
> nominal number for modern chips and "typical" applications is 3 ns).
> The interpretation is to allow time after the clock edge for each
> flip-flop (that has an asynchronous input) to "choose" which state
> to land in.


The original question didn't ask about metastability at all.  It seemed 
to me that he was trying to exactly predict the timing margins required 
to make the design work.

> In a private e-mail to me, Peter Alfke both complained that this
> approach is flawed (because the metastability delay is statistically
> unbounded, and of course he's right) and gave me the 3 ns number above
> (conservative for "all but perverse cases").  

(snip)

> An alternative approach (I have seen other people do this) is to put
> two stages of flip-flops on all clock-domain crossings, and _assume_
> there is a ton of slack between them.

Well, you have a whole clock cycle of slack between them.  Because of 
the exponential, that is usually good enough.  If you are close to where 
it isn't, synchronous parts of the design will have metastability 
problems, too!

If your design will not fail in 1e100 years, is that good enough?

OK, today is tuesday, what day of the week will it be in 1e100 days? 
Only ordinary calculators need to be used in figuring this out.

-- glen