Re: Quartus generics and vhdl

JohhnyNorthener wrote:
> P L E A S E  somebody help.  I have a design of mixed .gdf and .vhd
> files that
> were created in MaxPlusII, which I have imported it into Quartus II
> v3.0 SP2.
>
> What I am trying to do is to convert the complete design into VHDL
> ONLY
>
> The reason for doing this is so that i can do a functional simulation
> of my design prior to synthesising it - synthesis currently takes 4
> hours ! !

Sounds like a good reason to write some code.
The fixed-pc license includes modelsim, which
should handle this job for you.

>     - currently, the way i am creating a VHDL ONLY representation of
> my design
>     (without synth'ing) is by 'create HDL design file for current
> file' on      every block diagram i have.

Consider using the block diagrams only
as a guide to write your own vhdl synth code.
Do a bit at a time using a modelsim compile
to check syntax.

Write a simple testbench before attempting synthesis.

If rewriting the synth code is too much trouble,
consider writing a modelsim testbench only for
your existing .vho netlist.


 -- Mike Treseler