Quartus generics and vhdl

P L E A S E  somebody help.  I have a design of mixed .gdf and .vhd
files that
were created in MaxPlusII, which I have imported it into Quartus II
v3.0 SP2.

What I am trying to do is to convert the complete design into VHDL
ONLY

The reason for doing this is so that i can do a functional simulation
of my design prior to synthesising it - synthesis currently takes 4
hours ! !

The problems I am having with Quartus are :- 

    - currently, the way i am creating a VHDL ONLY representation of
my design
    (without synth'ing) is by 'create HDL design file for current
file' on      every block diagram i have.  with quite a few block
diags this is getting VERY
    ANNOYING, slow and highly prone to error. does anybody know how to
do it better ?


     - generics dont work properly. declaring a parameter that defines
the
     generic works fine...so long as you dont want the generics to be
inhereted
     from the hierarchical level above - this is where the problems
arrise.  if
     i want the generic to be inhereted then i have to leave the
'value' box for
     the parameter empty, however this causes the generic clause to be
empty
     when i then create a HDL design file of my block diagram.