Re: Design analyse methods

"ALuPin" <[EMAIL PROTECTED]> wrote in message
news:[EMAIL PROTECTED]
> Dear Sir or Madam,
>
> when tyring a complex FGPA design on real hardware
> what possibilities do exist to analyse the design ?
> Of course one possibility are debug pins but the problem
> is that their availableness is not always given.
>
> Simulation might be a good first step in order to prove
> first correct functionality but what if there are
> some components which cannot be reproduced my models so
> easily?
> Are their any tools (for Altera Cyclone FPGA) which allow
> to observe the diffent signals live (not simulation!) without having
> to route them to output pins (which are of limited number anyway,
> apart from that
> the timimg may be changed in an unmeant way) ?
>
> Thank you for your information and help.
>
> Best regards
>
> Andre


So, you have an FPGA on a board and you want to know the value of signals
within that FPGA, but you don't want to use any external pins? Hmmm.

Two sensible choices -
SignalTap - Not used it, but at a guess it uses internal RAM to store
signals, then communicate them via JTAG back to the host PC.
VITAL, or Gate Level simulation. OK, its simulation, but (in theory) it is
the Place and Route tool's view of what it has just placed and routed,
complete with ps accurate delays. You should do a gate level sim anyway,
just in case your design has been broken by one of the tools along the way.


--
Ian Poole, Consultant

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