Re: Exact Timing Constraints vs. Over-Constraining

In article <[EMAIL PROTECTED]>, Phil Hays wrote:
> I try to enter the constraints that exactly match the timing that the
> design will need to function, including board delay, loading delay,
> clock jitter and clock skew.

Don't forget metastability slack.  In theory it does not apply to the
purely synchronous nets; in practice I don't want to go through the
work of separating them out, and it's a good excuse to add one more
conservative assumption.

       - Larry