Re: XC9500 design does not fit into Coolrunner

"Klaus Falser"  wrote
>
>
> No, for my first try I did not give any constrains, whether for pins nor
for the
> timing.
> The I/O interface is bus-like, so the I/O lines share all the same OE.
> From my experience with the 9500's I have seen there are sometimes
problems when
> creating a too large multiplexor, which comes from the available Product
terms per
> macrocell.
> For instance, if you have a bus and you want to read back from more
> than 5 different registers, which implies a multiplexor before the
output-pins,
> you have to distribute your pins carefully, since every macrocell with an
output pin
> needs to steel PT from their neighbours.
> Coolrunner CPLD seems to have less PT inputs per macrocells, but give
enough
> macrocells and without placing constraint I did expect some fit.

Comparing the two RPT files should give some guidelines ?.
It is common for fitters to give better info, for a design that fits, so
'approaching the problem from (just) below' can be much more productive.
When you have a partial design fitting, check the correct globals have
been mapped OK. Missing a global resource can balloon usage.
Sometimes the device package can have an influence - if there is more than
one
choice, get a report file for each package.
-jg