Re: XC9500 design does not fit into Coolrunner

In article <[EMAIL PROTECTED]>, 
[EMAIL PROTECTED] says...
> Klaus Falser wrote:
> > Hello,
In article <[EMAIL PROTECTED]>, you say...
> Klaus Falser wrote:
> > Hello,
> > 
> > I have a rather large design for a XC95288XL which consumes 276 macrocells 
> > of 288 possible.
> > Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's 
> > I tried to stuff the design into a Coolrunner II chip to look how it 
> > would behave.
..snip .
> Have you constrained the design (pin assignments, etc)? What
> is the fitter complaining about?
> 
> There are some hard limits, like less OE lines than there are
> outputs to a block. If, for instance, you are trying to create
> a large GPIO device with more than 4 I/Os per block (8 are
> possible) it won't work.
> 
> Kind regards,
> 
> Iwo
> 
> 

No, for my first try I did not give any constrains, whether for pins nor for the 
timing.
The I/O interface is bus-like, so the I/O lines share all the same OE.
>From my experience with the 9500's I have seen there are sometimes problems when 
creating a too large multiplexor, which comes from the available Product terms per 
macrocell. 
For instance, if you have a bus and you want to read back from more 
than 5 different registers, which implies a multiplexor before the output-pins, 
you have to distribute your pins carefully, since every macrocell with an output pin
needs to steel PT from their neighbours.
Coolrunner CPLD seems to have less PT inputs per macrocells, but give enough 
macrocells and without placing constraint I did expect some fit.    

Best regards
-- 
Klaus Falser
Durst Phototechnik AG
[EMAIL PROTECTED]