jitter in Virtex2 DCM

The VirtexII data sheet requires an input jitter for 
the DCM smaller than + or - 300 ps (in Low Frequency Mode).
Obviously this ensures the proper behavior across all
permitted frequencies and modes.

In my case I have an input clock with 1ns of pk-pk jitter, but
it is a 40 MHz clock, that I only need to shift by 90 (clk90),
and to multiply by 2 (clk2x) other than having a locked version
(clk0) of the original clock.
How can I verify if it still works reliabily ?
Or is the going to DCM loose lock ?
Or will the phase relationships btw the output clocks not met ?
-- 
Tullio Grassi