Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM

"Martin Euredjian" <[EMAIL PROTECTED]> wrote in message
news:[EMAIL PROTECTED]
> "Yttrium" wrote:
>
> > you're right it is a bad design, but like i mentioned in my subject, i'm
> > just a newbie getting to know VHDL and FPGA's...
>
> To be sure it went across correctly, I wasn't criticizing you
> personally...just wanted to stress that this isn't a good idea in general.

Yes, i know ;-) ... just wanted to stress that fact hehe ...

>
> Think hardware design without an FPGA.  Most of the same rules apply.
>

indeed indeed, i think the main problem was getting used to the fact that
VHDL is a programming language but it designs hardware. so you tend to think
to much in a software way, but i'm learning not to :-)

> A clock mux on a V2 will switch between clocks cleanly.  That's a resource
> you can use.  However, you need to have the right reasons to do so.  If
it's
> simply to keep a FF from latching an input, it's probably safe to say that
> this would be a bad idea.
>
>

i couldn't use the solution with the ce FF because the system clock is on
the same clock as on of the output clock signals from the DCM so that would
have divided the frequency by 2. but i looked at the BUFGCE component and
that seems to have solved the problem (warning) but i'm still looking if the
BUFGMUX. but for now the BUFGCE seems to be the solution ...

thanx, for the comments and help,

kind regards,

Yttrium

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> Martin Euredjian
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