Re: 5V I/O with 1.8V Core

In article <[EMAIL PROTECTED]>,
Jim Granville <[EMAIL PROTECTED]> wrote:
>> Any processing rule which had two Vts for the different transistors
>> would probably require a fairly substantial spacing between the two
>> types.
>
>Why ?   Sure, more steps will be needed - but spacing ?

I'ts just an observation that anything special tends to require
greater spacing as well as greater steps.  I don't have/haven't seen
any actual design rules with multiple Vt threshholds, but the most
sophisticated I've delt with is .18 micron.

Additionally, for all but FPGA, mixing high Vt and low Vt transistors
very close would not be a huge benefit compared with just having the
two.
-- 
Nicholas C. Weaver                                 [EMAIL PROTECTED]