Re: Dual port RAM for Xilinx

It is possible to use single bit signals al long as you define them as a
std_logic_vector (0 downto 0). This vector can be converted to a single
signal by the statement
signal <= vector(0);

Mark

"Erik Markert" <[EMAIL PROTECTED]> schreef in bericht
news:[EMAIL PROTECTED]
> Hello Tobias,
>
> Tobias Möglich wrote:
> > Hello,
> >
> > Is there someone who has experiences with designing a dual port RAM.
> > I use the device Spartan-IIE (XC2S300E). But it should be simular with
> > other devices (e.g. Virtex, Spartan 3, etc)
> > I know there is a Synthesis Template in "Xilinx ISE Foundation".
>
> I used that template without problems. But I assume that you can't use
> single-bit signals as RAM-data-inputs.
>
> some Code:
>
> multibit <= singlebit1 & singlebit2;
>
> RAM_P:PROCESS(clk)
> BEGIN
>   if rising_edge(clk) then
>    if write = '1' then
>     ram(writeaddress) <= multibit;
>    end if;
>    readaddress <= read_address_in;
>   end if;
> END PROCESS;
>
> data_out <= ram(readaddress);
>
> Synthesis now builds block RAM (synchronous read). For distributed RAM
> read can be asynchronous.
>
> HTH
>
> Erik
> -- 
> \\Erik Markert - student of Information Technology//
>   \\     at Chemnitz University of Technology     //
>    \\   TalkTo: [EMAIL PROTECTED]   //
>     \\      URL: http://www.erikmarkert.de      //
>