Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM

Martin Euredjian wrote:

> "Yttrium" wrote:
>
>
> > ddr_clkx2 <= ddr_clkx2_out and locked;
>
>
> That's BAD design, as the the tools are saying.  

Agreed, it is not good FPGA design.

But the crazy thing is that Xilinx has the ability to do this relatively 
safely... but they don't seem to push it very hard and the tools don't 
automatically use it for you.  Check out the BUFGCE in the V2 and S3 
devices.

Not portable, but usable.

   Marc