Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM

"Yttrium" wrote:

> ddr_clkx2 <= ddr_clkx2_out and locked;

That's BAD design, as the the tools are saying.  How bad?  If someone
working for me did that they'd be on the street faster than the PERIOD
constraint on the design.

Do a newsgroup/google/yahoo search for "gated clock" for more info.


> so how should i implement it and what they mean with CE pin? well i know
> what they mean but how should i implement it in VHDL for a VIRTEXII?

This is right out of the "Language Templates" found under the "Edit" menu:

-- D Flip Flop with Clock Enable
--     CLK: in STD_LOGIC;
--     ENABLE: in STD_LOGIC;
--     DIN: in STD_LOGIC;
--     DOUT: out STD_LOGIC;

process (CLK)
    begin
        if (CLK'event and CLK='1') then
    if (ENABLE='1') then
             DOUT <= DIN;
            end if;
        end if;
end process;



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Martin Euredjian

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