Re: IDE Ultra DMA on a SPARTAN II

hi, 
for PIO mode, the DIOR (DDMARDY?) is the data strobe. 20ns setup, 5ns hold time is guaranteed by device.  At the host side, if you use spatan or virtex, I believe xilinx FPGA does not required hold time and you have plenty of setup time already. 
For ultra DMA mode, its more tricky. 
Data is strobed by both edges of DSTROBE (DMA in)

I believe ATA-6 spec do not recommend to strobe data directly with DSTROBE. Instead using another clock "synchronized version of DSTROBE" (thats what they said : ) to strobe data during DMA in. You may look at 6 asynchronous circuits
by Petter at xilinx web site for reference,

good luck