Re: XC9500 design does not fit into Coolrunner

Klaus Falser wrote:
> Hello,
>
> I have a rather large design for a XC95288XL which consumes 276 macrocells 
> of 288 possible.
> Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's 
> I tried to stuff the design into a Coolrunner II chip to look how it 
> would behave.
>
> However, I was not able to make it fit even in a 512 macrocell device.
> Timing should not be so tight, it has to run at 8 MHz clock, but the 
> timing analyzer gives me 17-18 MHz on the slowest 10 ns device.
>
> Can anybody which know's the XCR2 better than me give me a hit where 
> to pay attention?
> How can I see from the report where the fitter has a problem?
>
> Thanky you very much
>        

Have you constrained the design (pin assignments, etc)? What
is the fitter complaining about?

There are some hard limits, like less OE lines than there are
outputs to a block. If, for instance, you are trying to create
a large GPIO device with more than 4 I/Os per block (8 are
possible) it won't work.

Kind regards,

Iwo