Re: 5V I/O with 1.8V Core

Source-to-drain leakage is caused byoff- transistors not completely
turned off.
This is caused by a Vcc/Vthreshold ratio that is not ideal.
Fundamentally, it is a trade-off between significantly higher leakage
current at significantly higher speed, vs. both of these parameters
significantly lower. There is no magic trick (at least not yet, and not
even on the horizon).

And for most (not all!) FPGA applications, speed is king, and leakage
current is whatever it is. 
This may change one day...

Peter Alfke
========================
Tullio Grassi wrote:
> 
> On Tue, 25 Nov 2003, Austin Lesea wrote:
> 
> > THE problem today  however is drain source leakage.
> 
> Out of curiosity there is a design approach that completly kill
> the Source-to-drain leakage; it's used in radiation environments.
> Unfortunatly all other performances are greatly reduced.
> It's published in Nucl. Instrum. Methods Phys. Res., A 439 (2000) 349-60
> 
> http://weblib.cern.ch/cgi-bin/ejournals?publication=Nucl.+Instrum.+Methods+Phys.+Res.,+A&volume=439&year=2000&page=349