Usenet.com

www.Usenet.com

Group Index

Comp Thread Archive from Usenet.com

<-- __Chronological__ --> <-- __Thread__ -->

Re: Slightly unmatched UART frequencies



Joel Kolstad wrote:
> 
> Hal Murray <[EMAIL PROTECTED]> wrote:
> >> You bright up a good subject, and you're absolutely correct that if you
> >> continuously send data from one serial port at 9600.01bps to a receiver
> >> at 9600, sooner or later there must be a buffer overflow. ...
> >
> > I think you are missing a key idea.  The receiver has to make
> > sure that it will tolerate early start bits.  That is the receiver
> > has to start looking for a new start-of-start-bit right after
> > it has checked the middle of the stop bit rather than wait unitl
> > the end of the stop bit to start looking.
> 
> Unless your (slightly slower) transmitter also has the capability of
> producing shortened start (or stop) bits, how those this approach 'fix' the
> problem?  If the date rates are, say, 9601 received BPS and 9600 transmitted
> BPS, detecting early start bits just buys you one extra bit interval before
> your overrun your buffers, doesn't it?

I think I just understood what is wrong with my thinking.  I was only
looking at one direction.  The problem the OP has is that he is looping
back the received data and retransmitting it at the same slow(er) rate
the receiver is using.  Since the transmitter must use a full 10 bits,
then the buffer between the receiver and transmitter will overflow at
some point.  

This is a problem that is found in communications systems.  All units
must run at the same rate, but may use a different reference.  So if
they receive data at 8.0000 kHz and try to DAC it at 7.9999 kHz, about
once per ten seconds there will be a byte too many and a sample will
have to be dropped.  This will cause a noticable click or other
distortion of the voice.  

Some systems try to buffer this out, but that only postpones the
problem.  Most systems use a common reference that is very accurate and
stable.  Then the ADC and DAC clocks must be sync'd to the reference.  I
worked on a system that used a bendable VCXO to establish the 8 kHz
rate.  As the buffer data count varied from half full, the VCXO rate was
increased or decreased by small amounts to keep the average rates
matched.  

In the case of the OP, the first channel can use two stop bits and the
echo channel can use one stop bit.  This may not be pretty, but it will
work.  

-- 

Rick "rickman" Collins

[EMAIL PROTECTED]
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



<-- __Chronological__ --> <-- __Thread__ -->


Usenet.com



Please check out one of the premium Usenet Newsgroup Service Providers below for access to Usenet.