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Re: Slightly unmatched UART frequencies



Joel Kolstad wrote:
> 
> Hal Murray <[EMAIL PROTECTED]> wrote:
> >> You bright up a good subject, and you're absolutely correct that if you
> >> continuously send data from one serial port at 9600.01bps to a receiver
> >> at 9600, sooner or later there must be a buffer overflow. ...
> >
> > I think you are missing a key idea.  The receiver has to make
> > sure that it will tolerate early start bits.  That is the receiver
> > has to start looking for a new start-of-start-bit right after
> > it has checked the middle of the stop bit rather than wait unitl
> > the end of the stop bit to start looking.
> 
> Unless your (slightly slower) transmitter also has the capability of
> producing shortened start (or stop) bits, how those this approach 'fix' the
> problem?  If the date rates are, say, 9601 received BPS and 9600 transmitted
> BPS, detecting early start bits just buys you one extra bit interval before
> your overrun your buffers, doesn't it?

No, by looking for the start of next word before the last word is
complete, the receiver can receive data faster than you would calculate
given the clock speed and the bit count.  The receiver can receive data
in 9.5 bit times per byte rather than the 10 bit times per byte the
transmitter takes to send them.  That is where the 0.5 bit or about 5%
rate mismatch numbers come from.  

-- 

Rick "rickman" Collins

[EMAIL PROTECTED]
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



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