Re: 5V I/O with 1.8V Core

"Austin Lesea" wrote
> Jim,
>
> The big question is:  "would anyone want to pay for a FPGA that is 1/2
> the speed but 1/10 the leakage?"

Agreed.

If you can make it "a FPGA that is 1/2 speed, but 1/1000 leakage", it's a
better
question.
This brings it into line with ASIC, the uC example quoted, and even the
latest CPLDs

Or, you could ask "Would you like our next generation FPGA to be 2x faster,
or appx the same speed and 1/1000 of the standby  current ?"

The typical customer will, of course, reply "I'd like both" :)

 I can recall a time when FPGAs were chosen as the low static Icc prog.
logic solution,  and CPLDs were the power-hogs -  today that situation
seems to have reversed.

> As for Intel, great PR, but they have absolutely no way that they have
> announced to reduce drain source leakage.  That big PR splash was for
> "gate leakage" which is a small problem today.  THE problem today
> however is drain source leakage.

Some of the strained silicon plots I saw looked an improvement
- incremental, but a step in the right direction...

It's on the radar, so improvements will come....

-jg