Re: Slightly unmatched UART frequencies

Here is my simple analysis:
There are two very different situations:

If the transmitter clocks slower than the receiver, there is no problem
on the receive end, as long as the error inside the word does not exceed
half a bit time.

If the  transmitter clocks faster than the receiver, the receiver has to
be able to resynchronize after only half a stop bit (which may be touchy).

Peter Alfke
==============================
glen herrmannsfeldt wrote:
> 
> juergen Sauermann wrote:
> 
> (snip)
> 
> > I still do not believe, though, that inserting idle time one way or the
> > other (including cutting the transmitter's stop bit) is a solution.
> > Consider the following:
> >
> > Left side: Slow (9600 Baud)
> > Right side: Fast (9700 Baud)
> >
> > Both sides use e.g. 8N2 for Tx and 8N1 for Rx.
> >
> > At some point in time, Left see's its buffer filling up and hence skips
> > a few stop bits here and there (using 8N1) in order to compensate this.
> > Left is now faster that Right, despite of the clock rates.
> >
> > As a consequence, Right sees its buffer filling up and skips stop bits
> > (using 8N1) as well.
> >
> > This continues until both sides transmit with 8N1 all the time; at this
> > time Left will loose data.
> 
> As far as I know, asynchronous transmission was intended to be between
> two devices, such as a terminal and a computer, though more likely two
> terminals in the early days.
> 
> The two stop bits were required by machines that mechanically decided
> the bits.  (The Teletype (R) ASR33, for example.)  Using stop bits as
> flow control seems unusual to me.
> 
> Electronic UARTs (no comment on mechanical ones) sample the bit at the
> center of each bit time.  For a character with no transitions (X'00' or
> X'FF') timing error can accumulate for the duration of the character.
> The STOP bit is the receivers chance to adjust the timing, and start
> over with the new START bit.
> 
> With a 5% timing error, which is very large for a crystal controlled
> clock, the stop bit could start 0.45 bit times early, but the receiver
> will still detect it at the right time, and be ready to start the next
> character.
> 
> The timing for each character is from the leading edge of the START bit.
> 
> This allows for difference in the bit clock rate between the transmitter
> and receiver.   It is unrelated to any buffering or buffer overflow
> problems that may occur.
> 
> -- glen