Re: Slightly unmatched UART frequencies

"Philip Freidin" wrote
>
<snip>
> And Philip writes:
> Modifying the local transmited character to be a non-standard length
> by changing the length of the stop bit on the fly as buffer
> over-run is about to occur is not a good idea, as you don't
> know the details of how the receiver that is listening to it was
> designed, and it may not be very happy to see the next start bit
> before it is finished with what it expects is a full length stop
> bit, but it is not.

UARTs look for the START edge, from the _middle_ of the STOP bit.
With x16 clocking, typically that gives 8 possible time slots for earlier
start.

 I would agree that a half-bit jump in STOP, as the OP first suggested,
is NOT a good idea, but fractional (1/16 quantized ) STOP changes are
valid and safe.

<snip>
>
> BUT this is not a solution to the original poster's problem!
> The problem still exists because the remaining .5 bit is still
> going to arrive, the data is being sent with a slightly faster
> clock than the transmitter is able to retransmit the character.
> If there is no line idle time between the end of the inbound
> stop bit and the next inbound start bit, the system will
> eventually have an over-run problem, no matter how big the
> input buffer. The closer the two clock rates, and the bigger
> the buffer, the longer it takes to happen, but it will happen.

 Yes, true if the stop bit is 'whole bit' quantized.
CAN be avoided if  the TX can move the START edge as
needed, both left and right, in 1/16 steps. Something like
+/-4 sixteenths would leave design margin.

> F)
> Be sneaky. Most UARTs can be set for 1 , 1.5 , or 2 stop bits.
> Set the far end transmitter for 8N2 (1 start, 8 data, 2 stop).
> Set your receiver and transmitter for 8N1 (1 start, 8 data, 1 stop).
> This works, because stop bits look just like line-idle. This
> effectively implements (B), but is localized to the initialization
> code for the far end transmitter.

Yes, by far the simplest, and most practical solution.

However, this is comp.arch.fpga, and here we can design any UART we like,
including one that can handle 100% traffic loading, single stop bits, and
1-2% region clock skews. !  :)

 To illustrate this, look at the SC28C94 UART data, this from info
on their 16 possible STOP BIT options:

MR2[3..0] = Stop Bit Length
0 = 0.563
1 = 0.625
2 = 0.688
3 = 0.750
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
8 = 1.563
9 = 1.625
A = 1.688
B = 1.750
C = 1.813
C = 1.875
E = 1.938
F = 2.000

-jg