Re: How many dedicated clock pins EP20K1500EBC652 device?

Vaughn,

Thank you very much for your help!

I was confused when reading apex.pdf: somewhere says 8 "dedicated
clock and input pins", somewhere says 4 "dedicated clocks". Now I know
the difference is that 4 "fast input pins".

One question: to access the "dedicated fast resources", do I simply
define an internal net as "global signal"? During compilation, I saw
msgs like "promote signal XXX to global signal automatically". Does it
mean it uses dedicated fast resources for that signal already?

> 
> The two resources aren't much different.  The dedicated clocks are
> driven by dedicated input pins, while the fast dedicated networks can
> be driven by bidirectional IOs or internal signals from the FPGA
> fabric.  So most people just consider this 8 dedicated clocking /
> asynchronous clear networks.

I just did an experiment: use pin Y34 (dedicated clock pin) to drive a
few small modules and I see clock skew of less than 0.1 ns; then I use
pin B19 (fast1) to drive the same modules, this time I see clock skew
of more than 1.1 ns;  (skew observed from layout/floorplan view)

Do you think this skew will be too large for the hold-time of the
flip-flops on fpga?

> 
> clk1p and clk2p aren't connected together, so you can send 4 signals
> in through the dedicated clock pins.

I wasn't clear in my first post: the FPGA is sitting on a DSP board,
so the clk1p and clk2p are connected. I probably will cut them apart.

> 
> The FAST pins drive the dedicated FAST networks, which can be used as
> another 4 clock networks:

Same concern as I mentioned above: is > 1.1ns skew too large for them
to be used as clock networks?

thanks!

Yi