Re: Slightly unmatched UART frequencies

"Hal Murray" <[EMAIL PROTECTED]> wrote in message
news:[EMAIL PROTECTED]
> >You bright up a good subject, and you're absolutely correct that if you
> >continuously send data from one serial port at 9600.01bps to a receiver
at
> >9600, sooner or later there must be a buffer overflow. ...
>
> I think you are missing a key idea.  The receiver has to make
> sure that it will tolerate early start bits.  That is the receiver
> has to start looking for a new start-of-start-bit right after
> it has checked the middle of the stop bit rather than wait unitl
> the end of the stop bit to start looking.

Correct. If you really must tolerate continuous streams, with no data loss,
and only a single stop bit, then you must actually be able to 'pass on' data
at whatever average rate it comes in at.
Some UARTS have the idea of fractional TX stop bits to allow this, most just
choose
2 stop bits to give margin.
Receive should ALWAYS start looking for START at the middle of STOP.
( but chips do not always get this right :)

The OP's idea of a full half bit is a coarse example, that can force an
error, as it
jumps right to the limit

Since this was using 16x BAUD clocking, you can quantize to 1/16 of bit
time,
or in appx 0.625% steps.  4 of these is 2.5%, or 1/4 bit, that tolerates to
9840 Baud
If you don't want to use up all the error budget at one end, that's about
the limit.
( 1/4 bit at each end, or a tad less, if you use 3 slot vote sampling )

This is why most uC with trimmed on-chip OSCs specify 2.5% or 2% precision.

Since this a PLD device, you could watch for TX buffer phase, and nominally
send
a full STOP bit, but if the phase indicates margin problems (incomming
faster than outgoing)
you can decrement the STOP bit in 1/16 fractions - or you could force 15/16
wide STOP bit
and use a crystal, and keep the logic simpler. (tolerates to 9660 Baud, 100%
traffic )

A purists design would also extend STOP bits fractionally, (17/16 at ip
<9600Bd true)
so a sudden  whole bit jump did not occur. That could cause problems if a
number
of these are in a chain, and a system with phase jitter, that averages 9600,
but is
sometimes faster, sometime slower might also exist.

Makes the idea of a Continuous BAUD test pattern generator interesting  -
one that can
generate controlled errors on both sides of true, and with dithering.

Good student project :)

-jg