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> When you say "your" UART, is this a design you did yourself in an FPGA? Yes, you're right I have my design runs on CPLD. However, the qestion is more in logic rather than implementation. The value 10% I have got from www.8052.com's forum where "Software Uart" is a hot topic. > If so you may not have designed the logic correctly. In order for the > receiver to synchronize to a continuous data stream, it has to sample > the stop bit in what it thinks is the center and then *immediately* > start looking for the next start bit. This will allow a mismatch in > speed of almost a half bit minus whatever slack there is for the sample > clock rate. BTW, you are sampling at at least 8x the bit rate, right? I use 16x oversampling and check input values at middle of a bit (SampleCnt = 7). You suggest exactly what I have done. I think receiver part will work under any condition. But I need to know what should I do with transmitter module. As I attempted to explain, this half-bit solution cannot be used to synchronize transmitters. It is a bad idea to start transmitting next byte at the middle of the stop bit. It may fail listening device with slow clock as it reaches center of stop bit when start bit of next byte is being transmitted. On the other hand, if data is coming slightly faster transmitter should do something, otherwise I face buffer overrun condition. I understand that I can ignore the problem with transmitter module, it is receiver that should synchronize with transmitter. However, I had got buffer overrun problem until I used a trick described in my message (early transmit). It is defenetely not the problem with receiver because I have solved it right before got problem with transmitter's buffer overrun. And I want to know how should function correct logic; there should be a solution as commertial UARTs work without any problems. My UART is the first one where I've realized that it is at all possible to get a problem with slowly transmitting uart. Is now the problem become clearer?
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