Re: Slightly unmatched UART frequencies

valentin tihomirov wrote:
> 
> UART is used to transfer a byte in serial form bit-by-bit. I know that 10%
> deriviations in frequencies of transmitter and receiver are permissible. I
> was learnt that UARTs synchronyze at the falling edge (1to0) of start bit;
> hence, there should allow for transfer of a stream of bytes of arbitrary
> length.
> 
> I have developed a simple UART. It's receiver and transimtter run at 9600
> bps with 16x oversampling. Both receiver and transmitter have 1-byte buffer.
> To test the design I've created an echo device; it merely mirrors all the
> bytes sent to it back to the sender. It works fine with one of COM ports on
> my PC. Another COM port has its crystal running at a bit faster fundamental
> frequency. This causes a problem when it sends a long stream of bytes to my
> UART. 

When you say "your" UART, is this a design you did yourself in an FPGA? 
If so you may not have designed the logic correctly.  In order for the
receiver to synchronize to a continuous data stream, it has to sample
the stop bit in what it thinks is the center and then *immediately*
start looking for the next start bit.  This will allow a mismatch in
speed of almost a half bit minus whatever slack there is for the sample
clock rate.  BTW, you are sampling at at least 8x the bit rate, right?  

The max mismatch is not 10%, but a bit less that 5%.  In the field I
find that 2 to 3% mismatch is reliable, but any more and you can start
getting errors.  I guess the difference in theory and practice is
perhaps skew caused by the drivers.  

Does this make sense? 


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Rick "rickman" Collins

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