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Re: verification vs validation



hi rick, 

i am sorry for asking these type of trivial questions, 

let me be the first person to answer.

Difference between verification and validation

Validation and verification refer to the process of satisfying the
requirement, but the difference lies in the level of testing.

Verification refer to lower level of test, like testing of module,
interface etc. Verification tests are conducted by the developer.

Whereas validation occurs at the final stage prior to the acceptance
of a product for release. Validation tests are normally conducted by a
party that is independent of the developer (Quality Assurance or the
test group)

Emulation 

The process by which a device is built to work like another. For
example, a chip can be designed to emulate another model. The emulator
can be hardware, software or both



with regards
pradeep.g



rickman <[EMAIL PROTECTED]> wrote in message news:<[EMAIL PROTECTED]>...
> pradeep wrote:
> > 
> > Hi,
> > 
> > can any one give the difference between verification and validation ?
> > 
> Will I get credit for doing your assignments? 
> 
> > what is system level validation ?
> > 
> What is homework? 
> 
> > what is emulation ?
> 
> Why can't you read your text book?
> 
> 
> I don't normally answer posts that appear to be students asking for help
> with homework (or more correctly asking others to do the work for
> them).  But this is just too obvious.  
> 
> How about you read your book and write a couple of paragraphs on each of
> the above questions for us to critique?  Wouldn't that be more useful to
> you?  
> 
> -- 
> 
> Rick "rickman" Collins
> 
> [EMAIL PROTECTED]
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX



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