Re: avoiding GCLK

"Mastupristi" <[EMAIL PROTECTED]> schreef in bericht
news:[EMAIL PROTECTED]
> I use Xilinx ise web pack 6.1 sp 2.
>
> In my project I have a signal that is used as clock in only one flip
> flop.
> I have a constrain that place this signal on a generic iob.
>
> in the map process I obtain the following error:
> Using target part "2s50eft256-6".
> ERROR:MapLib:93 - Illegal LOC on IPAD symbol "din<0>" or BUFGP symbol
>    "din_0_BUFGP" (output signal=din_0_BUFGP), IPAD-IBUFG should only be
>    LOCed to GCLKIOB site.
>
> How can I force this signal to be placed in a non-GCLK pin?
>
> thanks
>
> -- 
> Mastupristi?
>
> Posted from X-Privat Free NNTP server - www.x-privat.org

The easiest way is probably to set the number of clock buffers in the proces
properties in the synthesis options - Xilinx specific options. This is the
number of clock buffers available to the synthesis process. If you set this
to '0' then no clock buffers are available for the synthesiser and none are
allocated. The clock buffers that you need in the rest of the design must be
created with library primitives.

I hope this helps,
Mark