vhdl construct problem

Hi, 
In my vhdl code, on construct is as follows 
case to_integer(addr) is

when to_integer(fifo1_base + fifo_status )=>

Where addr is signal of type unsigned(11 downto 0) and fifo1_base and fifo_status is constant of type unsigned(11 downto 0)

I tried to compile my code in Cadence tool(ncvhdl) and modelsim. In both the cases it said
for "when" statement
expecting a locally static statement.

But surprisingly the code got compiled successfully in quartus.
Where is the problem while trying to compile with cadence and modelsim? I am using vhdl 93 flag.