Re: Do I need to connect all Vref in a bank together?

On a sunny day (Tue, 18 Nov 2003 02:52:59 -0000) it happened
[EMAIL PROTECTED] (Hal Murray) wrote in
<[EMAIL PROTECTED]>:

>>hehe, I am using Vref as video input, trying to use the thing as AD.
>>On the other input of the comparator is an r2r ladder.
>
>Have you tried LVDS or other differential input modes?
Tried them all, very little difference I see.
I got rid of the instability using Austin Lesea's suggestion,
no more spikes.
Also changed some delay half a clock... so it is sampled a bit
later, to make sure the DA ladder has settled.
Seems fine on audio now, but with real fast clock still strange
things happen in video.
Timing is everything....
Also added nice sample and hold with a dual gate MOSFET,
most problems I have with webpack, unexpected things happen
not sure it is creating the same circuit I intended every time.
This is the biggest time factor getting this to work perhaps.
For example I changed some timing by going from an @posedge
to an @negedge trigger in verilog, then it stopped working
altogether, then I brought out that pin to be able to scope what happens,
and then it worked, so something changed..... 
These thing are for me a hurdle to take to use FPGA.
Jan